(1) Field of the Invention
This invention relates generally to voltage regulators, and more particularly to low dropout (LDO) having a clipping of the output current.
(2) Description of the Prior Art
Low-dropout (LDO) linear regulators are commonly used to provide power to low-voltage digital and analog circuits, where point-of-load and line regulation is important. FIG. 1 prior art shows a typical basic circuit of a LDO regulator 4 having an input voltage Vi 1, an output voltage Vo 2, an input current Ii and an output current Io.
In order to prevent high current stress of the LDO's pass device, especially during start-up, it is important to limit the output current.
There are various patents disclosed to limit the output current of an LDO or correspondingly to limit the drive current of a pass device of an LDO:
U.S. Pat. No. 5,929,617 (to Brokaw) teaches an low dropout voltage regulator (LDO) drive reduction circuit detecting when the LDO's output voltage is going out of regulation due to a falling input voltage while the output is lightly loaded, and reduces the drive to the pass transistor in response. This action prevents the LDO's ground current from rising unnecessarily. The drive reduction circuitry directly monitors the voltage across the pass transistor; when above a predetermined threshold voltage which is typically well-below the LDO's specified dropout voltage, the pass transistor drive is permitted to vary as necessary to maintain a specified output voltage. If the monitored voltage falls below the threshold voltage, indicating that the input voltage is falling and the output is lightly loaded, the drive reduction circuit reduces the drive current, which would otherwise get increased in an attempt to restore the output voltage. The transconductance of the novel drive reduction circuit is relatively high, making the region over which the drive reduction circuit is active small and permitting the threshold voltage to be precisely set.
U.S. Pat. No. 6,518,737 (to Stanescu et al.) discloses a low dropout voltage regulator with non-Miller frequency compensation. The LDO circuit has two wide-band, low-power cascaded operational transconductance amplifiers (OTAs): an error amplifier and a unity-gain-configured voltage follower. The unity-gain-configured voltage follower drives a gate of a power PMOS path transistor with a high parasitic gate capacitance. The wide-band, low-power OTAs enable the use of a single, low-value load capacitor with a low equivalent series resistance (ESR). A frequency compensation capacitor is connected in parallel with the upper resistor of a feedback network, which introduces a zero-pole pair that enhances the phase margin close to unity-loop-gain frequency.
U.S. Pat. No. 6,703,813 (to Vladislav et al.) discloses an LDO regulator being arranged to provide regulation with a pass device, a cascode device, a level shifter, an error amplifier, and a tracking voltage divider. The error amplifier is arranged to sense the output voltage and provide an error signal to the pass device via the level shifter. The level shifter changes the DC level of the error signal such that the pass device is isolated from damaging voltages. The cascode device is arranged to increase the impedance between the output node and the pass transistor such that the LDO regulator can sustain input voltages that exceed process limits without damage. The cascode device is biased by the tracking voltage divider. The tracking voltage divider adjusts the biasing to the cascode device such that a decreased input voltages result in lower impedance, and increased input voltages result in higher impedance.